lowRISC / lowRISC/opentitan

[chip-test] chip_sw_otp_ctrl_program

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Component:ChipLevelTest IP:otp_ctrl Priority:P2 SiVal:Autogen
Dominant language
SystemVerilog
Stars
3.6k
Forks
1.1k
Avg merge
2d 22h
Merged PRs (30d)
141

Description

### Test point name

chip_sw_otp_ctrl_program

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Contributor guide

Open the contributing guide

Research direction

No files or tests are named. Start by locating the existing chip_sw_otp_ctrl_program testpoint and checking whether an existing test covers most or all of it; then follow the checklist through device-side C, Bazel rules, host-side Rust, dvsim nightly regression, and SiVal execution. Done means the required components are implemented and the relevant regressions pass.

Written by the indexing model from the issue text.

Assessment

Tech stack
c, rust
Domain
embedded-iot, testing-qa
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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