[chip-test] chip_sw_otp_ctrl_entropy

### Test point name

chip_sw_otp_ctrl_entropy

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start with the chip_sw_otp_ctrl_entropy test point and check whether an existing test already covers most or all of it. Then determine the required device-side, Bazel, host-side, dvsim nightly, and SiVal regression work from the checklist. Done means the applicable checklist items are completed and linked PRs or issues are recorded.

Written by the indexing model from the issue text.