[chip-test] chip_sw_adc_ctrl_normal

### Test point name

chip_sw_adc_ctrl_normal

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start by locating the chip_sw_adc_ctrl_normal test point and checking whether an existing test already covers it. Then review the checklist for the device-side C component, Bazel build rules, host-side component, dvsim nightly regression, and SiVal coverage. Done means the applicable checklist items are completed and linked PRs or issues are recorded.

Written by the indexing model from the issue text.