[chip-test] chip_sw_all_escalation_resets

### Test point name

chip_sw_all_escalation_resets

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start by checking whether an existing test covers the chip_sw_all_escalation_resets testpoint. The payload calls for device-side C, Bazel build rules, a host-side component, and dvsim nightly regression coverage, plus relevant FPGA or silicon regression for SiVal. Done means the checklist items are completed and linked validation is passing.

Written by the indexing model from the issue text.