[chip-test] chip_lc_test_locked

### Test point name

chip_lc_test_locked

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

No files or test entry points are named. Start with the chip_lc_test_locked test point and determine the existing device-side, Bazel, host-side, and regression locations from the OpenTitan test infrastructure. Done means the checklist is completed, including relevant nightly, FPGA, or silicon regression coverage.

Written by the indexing model from the issue text.