[chip-test] chip_sw_lc_ctrl_key_div
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- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Test point name
chip_sw_lc_ctrl_key_div
### Host side component
Rust?
### Opentitantool infrastructure implemented
Yes
### Silicon Validation (SiVal)
Yes
### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310
### Contact person
### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by checking whether an existing test covers the chip_sw_lc_ctrl_key_div test point. Use the checklist to identify the required device-side C component, Bazel rules, host-side component, and dvsim or SiVal regression coverage. Done means the applicable checklist items are completed and linked to any related PRs or issues.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c, rust
- Domain
- build-system, embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100