[chip-test] chip_sw_lc_ctrl_otp_hw_cfg0

### Test point name

chip_sw_lc_ctrl_otp_hw_cfg0

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

No files, tests, or entry points are named. Start with the chip_sw_lc_ctrl_otp_hw_cfg0 test point and check whether existing coverage already includes it, then determine the needed device-side C, Bazel, host-side Rust, and dvsim regression work. Done means the checklist items are completed and relevant FPGA or silicon validation is running.

Written by the indexing model from the issue text.