[chip-test] chip_sw_entropy_src_fips_mode_health_tests

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### Test point name

chip_sw_entropy_src_fips_mode_health_tests

### Host side component
Rust?

### Opentitantool infrastructure implemented
Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start with the chip_sw_entropy_src_fips_mode_health_tests test point and determine whether an existing test already covers it. The checklist identifies the device-side C component, Bazel build rules, host-side Rust component, dvsim nightly regression, and FPGA or silicon regression as completion points; done means the relevant items are implemented and passing.

Written by the indexing model from the issue text.