[ci] FPGA agent pool bottleneck
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Component:CI
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Description
Currently each PR runs ~2.5 hours of tests that require a CW310 board. There are a limited number of CW310 boards available in CI (currently 6) which means that queues inevitably build up during busy periods.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the CI configuration and the FPGA/CW310 agent-pool setup. Measure where the six-board capacity creates queues, then define and validate a concrete approach that reduces PR wait time without removing the required CW310 tests.
Written by the indexing model from the issue text.
Assessment
- Domain
- ci-cd, embedded-iot, infrastructure
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100