[keymgr_dpe] Implement stress_all and stress_all_with_rand_reset test
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Component:Darjeeling
Component:DV
IP:keymgr_dpe
- Dominant language
- SystemVerilog
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Description
The `stress_all` and `stress_all_with_rand_reset` tests are currently disabled in the simulation config.
This issue here is to track its implementation.
Contributor guide
Research direction
Start by locating the simulation configuration entries for keymgr_dpe and the disabled stress_all and stress_all_with_rand_reset tests. Read the surrounding test setup and determine the implementation requirements; done means both tests are implemented, enabled in simulation, and pass.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100