lowRISC / lowRISC/opentitan

[mbx] Implement stress_all and stress_all_with_rand_reset test

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Component:Darjeeling Component:DV IP:mailbox
Dominant language
SystemVerilog
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Description

The `stress_all` and `stress_all_with_rand_reset` tests are currently disabled in the simulation config.
This issue here is to track its implementation.

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Locate the simulation config where the stress_all and stress_all_with_rand_reset tests are disabled, then inspect how nearby simulation tests are implemented and enabled. Implement both tests and verify that they run successfully in the simulation configuration.

Written by the indexing model from the issue text.

Assessment

Domain
testing
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
35/100

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