[spi_device] TPM return-by-hw flawed without hardware write support

@hcallahan-lowrisc is already working on this.

Since Sep 17, 2026.

### Description

The return-by-hw mechanism for TPM registers is missing hardware handling of writes, and it appears that makes it difficult to comply with the spec's timing for subsequent reads. With the SPI TPM spec, various FIFO interface registers require the ability to read the current value with only a single wait state, with the most critical register being TPM_ACCESS_x.

However, to process a write on time, a multi-tasking Firmware will need to receive an interrupt, process the command, and update the register in substantially less than 2 us (at 24 MHz SPI). The spec even calls out that the response to a write to TPM_ACCESS_x to request access should appear to host Software to happen "practically immediately." A write, followed by an immediate read of TPM_ACCESS_x is likely a very typical sequence, since this is needed to proceed with any TPM commands.