[chip-test] usbdev_sw_usbdev_pullup

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### Test point name

usbdev_sw_usbdev_pullup

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310

### Contact person

alees24

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [x] HJSON test plan updated with test name (so it shows up in the dashboard)
- [x] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Bazel target is //sw/device/tests:usbdev_pullup_test and should work on all platforms - DVsim, Verilator, CW FPGAs

Start by inspecting the existing //sw/device/tests:usbdev_pullup_test target and the checklist for usbdev_sw_usbdev_pullup. Determine which device-side C, Bazel, and SiVal regression items remain, then verify the target works on DVsim, Verilator, and CW FPGAs as stated.

Written by the indexing model from the issue text.