[chip-test] chip_sw_usbdev_vbus

### Test point name

chip_sw_usbdev_vbus

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310

### Contact person

_No response_

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [x] Device-side (C) component developed
- [x] Bazel build rules developed
- [x] Host-side component developed
- [x] HJSON test plan updated with test name (so it shows up in the dashboard)
- [x] Test added to dvsim nightly regression (and passing at time of checking)
- [x] For SiVal test cases, test is running relevant FPGA or silicon regression

Bazel test target is //sw/device/tests:usbdev_vbus_test and has been tested on DVsim, Verilator and CW FPGAs.

Start with the Bazel target //sw/device/tests:usbdev_vbus_test and review the checklist for the chip_sw_usbdev_vbus test point. Confirm that the device-side test, build rules, HJSON test plan, nightly regression, and SiVal coverage are present and passing on the listed targets; the issue indicates these items are already complete.

Written by the indexing model from the issue text.