[sival] All SiVal Tests
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Description
- PROD: https://github.com/lowRISC/opentitan/issues/20194
- DEV: https://github.com/lowRISC/opentitan/issues/21074
- RAW: https://github.com/lowRISC/opentitan/issues/21075
- RMA: https://github.com/lowRISC/opentitan/issues/21077
- PROD_END: https://github.com/lowRISC/opentitan/issues/21078
- SCRAP: https://github.com/lowRISC/opentitan/issues/21079
- TEST_UNLOCKED: https://github.com/lowRISC/opentitan/issues/21076
- TEST_UNLOCKED0: https://github.com/lowRISC/opentitan/issues/21080
- TEST_UNLOCKED1: https://github.com/lowRISC/opentitan/issues/21081
- NONE: https://github.com/lowRISC/opentitan/issues/21082
- TEST_LOCKED: https://github.com/lowRISC/opentitan/issues/21083
Contributor guide
Research direction
Start by reviewing the linked PROD, DEV, RAW, RMA, PROD_END, SCRAP, TEST_UNLOCKED, TEST_UNLOCKED0, TEST_UNLOCKED1, NONE, and TEST_LOCKED issues. Determine how these separate SiVal cases should be coordinated into the “All SiVal Tests” work; done means the complete set of linked cases is addressed.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100