[sival] test_locked_all_tests
Open
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
All TEST_LOCKED mode SIVAL tests
LC_MODE: TEST_LOCKED
hmac:
SV3:
- [ ] chip_sw_lc_ctrl_transitions | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
pwrmgr:
SV1:
- [x] chip_sw_pwrmgr_external_full_reset This is not a valid test, see #21654
Contributor guide
Research direction
Start with the SIVAL TEST_LOCKED checklist in this issue, focusing on the unchecked chip_sw_lc_ctrl_transitions entry under hmac and SV3. Determine the relevant implementation PR and testing details; it is done when the checklist records the implementation, test date, tester, and notes.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100