[sival] test_unlocked1_all_tests
- Dominant language
- SystemVerilog
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- 2d 22h
- Merged PRs (30d)
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Description
All TEST_UNLOCKED1 mode SIVAL tests
LC_MODE: TEST_UNLOCKED1
pwrmgr:
None:
- [x] chip_sw_pwrmgr_escalation_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes Not a valid test: https://github.com/lowRISC/opentitan/pull/21748
SV1:
- [x] chip_sw_pwrmgr_external_full_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes Not a valid test: https://github.com/lowRISC/opentitan/issues/21442
Contributor guide
Research direction
Review the TEST_UNLOCKED1 SIVAL checklist in this issue, beginning with the pwrmgr entries and the linked pull request and issue. Confirm which listed tests are valid and what remaining coverage is required; the issue is done when the checklist accurately reflects the completed TEST_UNLOCKED1 tests.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100