[sival] test_unlocked0_all_tests
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- SystemVerilog
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Description
All TEST_UNLOCKED mode SIVAL tests
LC_MODE: TEST_UNLOCKED
clkmgr:
SV2:
- chip_sw_clkmgr_div | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:ast_clk_outs_test_fpga_cw310_sival, //sw/device/tests:ast_clk_outs_test_fpga_cw310_sival_rom_ext, //sw/device/tests:ast_clk_outs_test_fpga_cw310_test_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_sival, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_sival_rom_ext, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_test_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_sival, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_sival_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_test_rom
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the clkmgr section and inspect the listed //sw/device/tests targets, especially the ast_clk_outs and clkmgr_external_clk_src tests for CW310 SIVAL and ROM variants. Determine which TEST_UNLOCKED SIVAL tests still need coverage; done means the checklist has implementation, pull request, test date, and tester details for all required tests.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100