[sival] rma_all_tests
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- Dominant language
- SystemVerilog
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- 2d 22h
- Merged PRs (30d)
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Description
All RMA mode SIVAL tests
LC_MODE: RMA
otp_ctrl:
SV3:
- [ ] chip_sw_otp_prim_tl_access | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
rv_dm:
SV2:
- [x] chip_rv_dm_ndm_reset_req | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_ndm_reset_req
- [x] chip_sw_rv_dm_jtag_tap_sel | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag_tap_sel
SV3:
- [ ] chip_jtag_csr_rw | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_jtag_mem_access | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_perform_debug | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_access_after_wakeup | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_sw_rv_dm_access_after_hw_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [x] chip_rv_dm_jtag | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag
- [ ] chip_rv_dm_dtm | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_control_status | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
uart:
SV3:
- [ ] chip_sw_uart_tx_rx_alt_clk_freq | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Review the SIVAL checklist for RMA mode, starting with the existing //sw/device/tests:rv_dm_ndm_reset_req, rv_dm_jtag_tap_sel, and rv_dm_jtag entries. Determine the implementation and test entry points for the unchecked OTP, debug, and UART cases; done means the applicable tests are implemented and tested, with their issue, PR, date, tester, and notes recorded.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100