[sival] test_unlocked_all_tests

All TEST_UNLOCKED mode SIVAL tests

LC_MODE: TEST_UNLOCKED

clkmgr:

SV2:

• chip_sw_clkmgr_div | GH Issue | Implementation PR | TESTED DATE | TESTED BY | chip_sw_ast_clk_outputs, chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0, chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0, chip_sw_clkmgr_external_clk_src_for_sw_fast_dev, chip_sw_clkmgr_external_clk_src_for_sw_slow_dev, chip_sw_clkmgr_external_clk_src_for_sw_fast_rma, chip_sw_clkmgr_external_clk_src_for_sw_slow_rma

hmac:

SV3:

• chip_sw_lc_ctrl_transitions | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_lc_test_locked | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes

otp_ctrl:

SV1:

• otp_ctrl_calibration | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes

SV3:

• chip_sw_otp_prim_tl_access | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes

pwrmgr:

None:

• chip_sw_pwrmgr_escalation_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes Not a valid test: https://github.com/lowRISC/opentitan/pull/21748

SV1:

• chip_sw_pwrmgr_external_full_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes Not a valid test: https://github.com/lowRISC/opentitan/issues/21442

rv_dm:

SV2:

• chip_rv_dm_ndm_reset_req | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_sw_rv_dm_jtag_tap_sel | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag_tap_sel

SV3:

• chip_jtag_csr_rw | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_jtag_mem_access | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_rv_dm_perform_debug | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_rv_dm_access_after_wakeup | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_sw_rv_dm_access_after_hw_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_rv_dm_jtag | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag
• chip_rv_dm_dtm | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
• chip_rv_dm_control_status | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes

Start with the unchecked SIVAL TEST_UNLOCKED entries, especially the hmac, otp_ctrl, and rv_dm test names, and compare them with the existing Bazel targets mentioned for rv_dm_jtag_tap_sel and rv_dm_jtag. The issue provides no source files or failing tests; done would require determining the missing implementations, testing them, and updating the checklist with implementation and test details.