[sival] dev_all_tests
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- SystemVerilog
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Description
All DEV mode SIVAL tests
LC_MODE: DEV
clkmgr:
None:
- [x] chip_sw_clkmgr_external_clk_src_for_sw | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:clkmgr_sleep_frequency_test_fpga_cw310_sival, //sw/device/tests:clkmgr_sleep_frequency_test_fpga_cw310_sival_rom_ext, //sw/device/tests:clkmgr_sleep_frequency_test_fpga_cw310_test_rom, //sw/device/tests:clkmgr_reset_frequency_test_fpga_cw310_sival, //sw/device/tests:clkmgr_reset_frequency_test_fpga_cw310_sival_rom_ext, //sw/device/tests:clkmgr_reset_frequency_test_fpga_cw310_test_rom
SV2:
- [x] chip_sw_clkmgr_div | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:ast_clk_outs_test_fpga_cw310_sival, //sw/device/tests:ast_clk_outs_test_fpga_cw310_sival_rom_ext, //sw/device/tests:ast_clk_outs_test_fpga_cw310_test_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_sival, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_sival_rom_ext, //sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test_fpga_cw310_test_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_sival, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_sival_rom, //sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_test_rom
pwrmgr:
None:
- [x] chip_sw_pwrmgr_escalation_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes Not a valid test: https://github.com/lowRISC/opentitan/issues/21442
rv_dm:
SV2:
- [x] chip_rv_dm_ndm_reset_req | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_ndm_reset_req
- [x] chip_sw_rv_dm_jtag_tap_sel | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag_tap_sel
SV3:
- [ ] chip_jtag_csr_rw | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_jtag_mem_access | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_perform_debug | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_access_after_wakeup | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_sw_rv_dm_access_after_hw_reset | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [x] chip_rv_dm_jtag | GH Issue | Implementation PR | TESTED DATE | TESTED BY | //sw/device/tests:rv_dm_jtag
- [ ] chip_rv_dm_dtm | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
- [ ] chip_rv_dm_control_status | GH Issue | Implementation PR | TESTED DATE | TESTED BY | Notes
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the existing targets under //sw/device/tests, especially the completed clkmgr, pwrmgr, and rv_dm entries, then identify how the unchecked SV3 SIVAL tests are implemented and executed. Done means the remaining listed tests have been addressed and their checklist status, implementation references, test dates, testers, and notes are recorded.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100