lowRISC / lowRISC/opentitan

[test-triage] Fix rstmgr_alert_info_test_fpga_cw310_sival

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#20,589 8 comments 0 reactions 3 assignees Assigned to @moidx View on GitHub
CherryPick:earlgrey_1.0.0 Component:DV Component:SiliconValidation Component:TestTriage
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Description

### Hierarchy of regression failure

Chip Level

### Failure Description

The rstmgr_alert_info_test_fpga_cw310_test_rom passes, but the _sival and _sival_rom_ext variants
fail. The failure is on round 3, when the test gets an unexpected flash_ctrl fatal alert. To reproduce it,
uncomment these tests from https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson
and run the test on a hyperdebug board with
bazel test //sw/device/tests:rstmgr_alert_info_test_fpga_cw310_sival

### Steps to Reproduce

bazel test //sw/device/tests:rstmgr_alert_info_test_fpga_cw310_sival

### Tests with similar or related failures

- [ ] //sw/device/tests:rstmgr_alert_info_test_fpga_cw310_sival_rom_ext

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