lowRISC / lowRISC/opentitan

[top_darjeeling] Wrong ePMP reset values

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Component:Darjeeling Component:MultiTop IP:rv_core_ibex
Dominant language
SystemVerilog
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Description

Description

Reset values for ePMP are currently shared between tops and located in hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh:

34'h20000000, // rgn 10 [MMIO: lo=0x2000_0000]
34'h33010000, // rgn 11 [MMIO: hi=0x3301_0000]
34'h00000000, // rgn 12
34'h000107fc, // rgn 13 [DV_ROM: base=0x0001_0000 size=0x1000 (4KiB)]

This file does not match Darjeeling definitions from hw/top_darjeeling/sw/autogen/top_darjeeling.h:

#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000
#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000
(...)
#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u
#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u

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First steps

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  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Compare the shared reset values in hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh with the Darjeeling address and size definitions in hw/top_darjeeling/sw/autogen/top_darjeeling.h. Trace how the ePMP regions use these values and update the reset configuration so it matches Darjeeling's definitions; done means the listed regions reflect the documented Darjeeling memory map.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
42/100

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