[chip-test] chip_sw_keymgr_derive_attestation
@andrea-caforio is already working on this.
Since Sep 30, 2024.
- Dominant language
- SystemVerilog
- Stars
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- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
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Description
### Test point name
chip_sw_keymgr_derive_attestation
### Host side component
Unknown
### OpenTitanTool infrastructure implemented
Yes
### Silicon Validation (SiVal)
Yes
### Emulation Targets
- [ ] None
- [X] CW310
- [ ] Hyperdebug + CW310
### Contact person
_No response_
### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.