[chip-test] chip_sw_lc_ctrl_debug_access

Test point name

chip_sw_lc_ctrl_debug_access

Host side component

Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation Targets

• None
• CW310
• Hyperdebug + CW310

Contact person

No response

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• HJSON test plan updated with test name (so it shows up in the dashboard)
• Test added to dvsim nightly regression (and passing at time of checking)
• For SiVal test cases, test is running relevant FPGA or silicon regression

Start at the chip-test entry for chip_sw_lc_ctrl_debug_access and check whether an existing test already covers most of the test point. Then use the checklist to identify the required device-side, Bazel, Rust host-side, HJSON, nightly regression, and SiVal work. Done means the test is implemented for CW310 and all applicable checklist items are complete.