[chip-test, sival] chip_sw_aes_force_prng_reseed test

### Test point name

[chip_sw_aes_force_prng_reseed](https://github.com/lowRISC/opentitan/blob/1dba0e6a94c84ace81b377b340a7a87a7c363f9a/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson#L176C9-L176C9)

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [ ] Hyperdebug + CW310

### Contact person

vogelpi

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate: 4

Start with the linked chip_aes_testplan.hjson test point and inspect existing coverage for chip_sw_aes_force_prNG_reseed. Then follow the checklist for the device-side C component, Bazel rules, test-plan update, and CW310 regression; done means the test runs successfully in the relevant regression.

Written by the indexing model from the issue text.