lowRISC / lowRISC/opentitan

[sim_dv,dpi] Connect opentitanlib to vcs and xcelium

Open
#20,220 0 comments 0 reactions 1 assignee View on GitHub

@matutem is already working on this.

Since Oct 27, 2023.

Component:DV Component:SiliconValidation Component:Software
Dominant language
SystemVerilog
Stars
3.6k
Forks
1.1k
Avg merge
2d 22h
Merged PRs (30d)
141

Description

### Description

Enabling opentitanlib to run against commercial simulators has a few important benefits:
- It can avoid custom top_level vseqs for a large number of simulation tests
- This means more tests can be run on either sim_dv or fpga, reducing the development load
- There is a number of tests that cannot be run from opentitanlib, like those that inject errors or need very precise timing
- It can enable running tests that fail against the hardware with little effort

This connection can be done leveraging the existing verilator transport, and the existing DPI it uses. There will be a need to customize some of the code, like the SV side of the DPI, and the way the transport starts verilator.

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.