[chip-test] chip_sw_alert_handler_ping_timeout

Nobody has claimed this yet.

### Test point name

[chip_sw_alert_handler_ping_timeout](https://github.com/lowRISC/opentitan/blob/3f65c2a534fc75ed43f3af438f01afc5232bfc2b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson#L154-L166)

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [x] Hyperdebug + CW310

### Contact person

@msfschaffner

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [x] Device-side (C) component developed
- [x] Bazel build rules developed
- [ ] Host-side component developed
- [x] HJSON test plan updated with test name (so it shows up in the dashboard)
- [x] Test added to dvsim nightly regression (and passing at time of checking)
- [x] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 0.5

Start with the chip_sw_alert_handler_ping_timeout test point in hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson and inspect the existing device-side C test and Bazel rules referenced by the checklist. Determine the missing host-side component and verify it against the CW310 and Hyperdebug + CW310 targets. Done means the host-side component is implemented and the test passes in the relevant regression.

Written by the indexing model from the issue text.