[chip-test] chip_sw_alert_handler_crashdump

Test point name

chip_sw_alert_handler_crashdump

Host side component

Unknown

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• None
• CW310
• Hyperdebug + CW310

Contact person

@msfschaffner

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• HJSON test plan updated with test name (so it shows up in the dashboard)
• Test added to dvsim nightly regression (and passing at time of checking)
• For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 0.5

Start with the chip_sw_alert_handler_crashdump test point in hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson and review the existing device-side C component, Bazel rules, and dvsim regression entry. Determine the missing host-side component for the CW310 and Hyperdebug + CW310 targets; done means the checklist item is implemented and the test passes in the relevant regression.