[chip-test] chip_sw_alert_handler_escalation_nmi_reset

### Test point name

[chip_sw_alert_handler_escalation_nmi_reset](https://github.com/lowRISC/opentitan/blob/3f65c2a534fc75ed43f3af438f01afc5232bfc2b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson#L48-L70)

### Host side component

Unknown

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [ ] Hyperdebug + CW310

### Contact person

@msfschaffner

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 2

Start with the linked chip_alert_handler_testplan.hjson test point and review the checklist to determine which existing test coverage and device-side, build, host-side, and regression components are missing. Coordinate with the listed contact before implementation. Done means the test point is implemented, recorded in the test plan, and running in the relevant CW310 and SiVal regressions.

Written by the indexing model from the issue text.