[chip-test] chip_sw_alert_handler_escalations

### Test point name

[chip_sw_alert_handler_escalations](https://github.com/lowRISC/opentitan/blob/3f65c2a534fc75ed43f3af438f01afc5232bfc2b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson#L27-L47)

### Host side component

Rust

### OpenTitanTool infrastructure implemented

Unknown

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [ ] Hyperdebug + CW310

### Contact person

_No response_

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 2

Start with the chip_alert_handler_testplan.hjson test point linked in the issue and check whether existing tests cover chip_sw_alert_handler_escalations. Determine the required device-side C, Bazel, and Rust host-side components, then update the HJSON test plan and verify the test in the relevant CW310 and regression flows.

Written by the indexing model from the issue text.