[chip-test] chip_sw_entropy_src_validation

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### Test point name

https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson#L165

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310

### Contact person

@vogelpi @andreaskurth

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start with the entropy-source test point linked in the issue and check whether existing tests already cover it. Completion requires the device-side C test, Bazel rules, the HJSON test-plan update, dvsim nightly regression coverage, and relevant CW310 or silicon regression execution.

Written by the indexing model from the issue text.