[chip-test] chip_sw_entropy_src_bypass_mode_health_tests

Test point name

https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson#L95

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• None
• CW310
• Hyperdebug + CW310

Contact person

@vogelpi @andreaskurth

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• Device-side (C) component developed
• Bazel build rules developed
• Host-side component developed
• HJSON test plan updated with test name (so it shows up in the dashboard)
• Test added to dvsim nightly regression (and passing at time of checking)
• For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 1

Start with the linked entropy source test-plan entry and check whether an existing test covers most or all of this test point. Use the checklist to determine the remaining device-side C, Bazel, HJSON, and dvsim regression work; done means the test is added and relevant regression coverage is passing.