[chip-test] chip_sw_usbdev_aon_wake_resume
Open
@pamaury is already working on this.
Since Feb 13, 2024.
Component:ChipLevelTest
Milestone:SV3
SiVal:TestRefactoring
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Test point name
chip_sw_usbdev_aon_wake_resume
Host side component
Rust
OpenTitanTool infrastructure implemented
Unknown
Silicon Validation (SiVal)
Yes
Emulation Targets
- None
- CW310
- Hyperdebug + CW310
Contact person
alees24
Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- Device-side (C) component developed
- Bazel build rules developed
- Host-side component developed
- HJSON test plan updated with test name (so it shows up in the dashboard)
- Test added to dvsim nightly regression (and passing at time of checking)
- For SiVal test cases, test is running relevant FPGA or silicon regression
estimate 2
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.