[chip-test] chip_sw_usbdev_tx_rx

### Test point name

chip_sw_usbdev_tx_rx

### Host side component

Rust

### OpenTitanTool infrastructure implemented

Unknown

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310

### Contact person

alees24

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [x] HJSON test plan updated with test name (so it shows up in the dashboard)
- [x] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 2

Bazel target is //sw/device/tests:usbdev_test and should work on all targets - DVsim, Verilator, CW FPGAs but note that on a physical host it requires the execution of a process such as 'cat /dev/ttyUSB' on the Host side to achieve character echo. The device-side code emits a simple test string and expects to receive that same string in response.

Start at the Bazel target //sw/device/tests:usbdev_test and inspect the existing USB device test and its host-side Rust coverage. Check the HJSON test plan and nightly dvsim entry, then verify the device emits a string and receives the same string through the CW310 or Hyperdebug setup. Done means the remaining device, build, host, and SiVal checklist items are completed and the test passes on the stated targets.

Written by the indexing model from the issue text.