[chip-test] chip_sw_usbdev_config_host
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Test point name
chip_sw_usbdev_config_host
### Host side component
None
### OpenTitanTool infrastructure implemented
None
### Silicon Validation (SiVal)
Yes
### Emulation Targets
- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310
### Contact person
alees24
### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression
> estimate 1
> estimate 0
[PR #21145](https://github.com/lowRISC/opentitan/pull/21145)
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing PR #21145, which is linked from the issue and may contain the implementation for chip_sw_usbdev_config_host. Use the checklist to identify remaining device-side C, Bazel, HJSON test-plan, and regression work; done means the listed SiVal and regression checks are completed.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 20/100