[chip-test] chip_sw_usbdev_mem

### Test point name

chip_sw_usbdev_mem

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [X] CW310
- [X] Hyperdebug + CW310

### Contact person

alees24

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 1

Start by checking whether an existing test already covers chip_sw_usbdev_mem. Then identify the device-side C component, Bazel build rules, and HJSON test plan entry needed for the CW310 and Hyperdebug + CW310 targets. Done means the test is included in the nightly regression and passes the relevant FPGA or silicon regression.

Written by the indexing model from the issue text.