[chip-level] chip_sw_sram_lc_escalation
@jwnrt is already working on this.
Since Oct 23, 2023.
- Dominant language
- SystemVerilog
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- Avg merge
- 2d 22h
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Description
### Test point name
chip_sw_sram_lc_escalation
### Host side component
None
### OpenTitanTool infrastructure implemented
None
### Silicon Validation (SiVal)
None
### Emulation Targets
- [ ] None
- [ ] CW310
- [x] Hyperdebug + CW310
### Contact person
@rswarbrick
### Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check whether one of the two existing chip-level tests (`chip_sw_all_escalation_resets`, `chip_sw_data_integrity_escalation`) can be tweaked to work in a si-val setting. If we're going to be executing from SRAM already, this will probably have to be performed on the retention sram.
- [ ] Develop the device-side (C) component (possibly by tweaking one of the above)
- [ ] Update hjson test plan with the test name (so it shows up in the dashboard)
- [ ] Get test running on relevant FPGA or silicon regression
> estimate 4
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
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