[chip-test] chip_sw_sysrst_ctrl_input_interrupt

### Test point name

[chip_sw_sysrst_ctrl_input_interrupt](https://github.com/lowRISC/opentitan/blob/cf8ffa811189c6c17285abae7eef19081213f739/hw/top_earlgrey/data/ip/chip_sysrst_ctrl_testplan.hjson#L47)

### Host side component

Rust

### OpenTitanTool infrastructure implemented

Yes

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [ ] CW310
- [x] Hyperdebug + CW310

### Contact person

crteja

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [x] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

> estimate 2