[chip-test] chip_sw_pattgen_ios

@pamaury is already working on this.

Since Oct 4, 2023.

### Test point name

[chip_sw_pattgen_ios](https://github.com/marnovandermaas/opentitan/blob/4a26de44480197ac42a911c4f19777ed8bcd73e3/hw/top_earlgrey/data/chip_testplan.hjson#L412)

### Host side component

Rust

### OpenTitanTool infrastructure implemented

Unknown

### Silicon Validation (SiVal)

Yes

### Emulation Targets

- [ ] None
- [ ] CW310
- [X] Hyperdebug + CW310

### Contact person

marnovandermaas

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Estimate updated from 2 to 4 after discussion with @pamaury on 5 October 2023:
> estimate 4