[chip-test] adc_ctrl_normal

### Test point name

[chip_sw_adc_ctrl_normal](https://github.com/lowRISC/opentitan/blob/6dd343e5e0b445eeecf16a966737e0b873ed8704/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson#L57C13-L57C36)

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

None

### Emulation Targets

- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

jdonjdon

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start with the chip_sw_adc_ctrl_normal entry in hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson. Use the issue checklist to determine which device-side, build, test-plan, and regression pieces are still missing. The work is done when the checklist items are completed and the test is passing in the required regression targets.

Written by the indexing model from the issue text.