[chip-test] adc_ctrl_debug_cable_wakeup

Nobody has claimed this yet.

### Test point name

[chip_sw_adc_ctrl_debug_cable_irq](https://github.com/lowRISC/opentitan/blob/6dd343e5e0b445eeecf16a966737e0b873ed8704/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson#L9C13-L9C45)
[chip_sw_adc_ctrl_sleep_debug_cable_wakeup](https://github.com/lowRISC/opentitan/blob/6dd343e5e0b445eeecf16a966737e0b873ed8704/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson#L33C13-L33C54)
### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

None

### Emulation Targets

- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

jdonjdon

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Start with the linked entries in hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson and check whether an existing test covers these test points. Use the checklist to scope the device-side component, Bazel rules, test-plan update, and regression work. Done means the test is added to the nightly regression and passing, with relevant FPGA or silicon validation completed if applicable.

Written by the indexing model from the issue text.