[regtool] hwext register with rw1c fields results in partial implementation.

### Description

I've been trying to get regtool to output sensible RTL that uses an external register with swaccess of `rw1c`. When running the following HJSON through the tool, I get a reg_top.sv that tries to use a non-existent `reg2hw.enable.re` signal.

I'm working around this at the moment by burning registers duplicating the external ones.

```hjson
{
name: BLOCK
cip_id: 1001
version: 1.1.1
regwidth: 32
registers:
[
{
skipto: 0x0
}
{
name: ENABLE
desc: ""
hwext: "true"
hwqe: "true"
hwre: "true"

fields:
[
{
name: EN
desc: ""
bits: 0
resval: 0
hwaccess: hwo
swaccess: rw1c
}
]
}
]
clocking:
[
{
clock: clk_i
reset: rst_ni
idle: idle
primary: "true"
}
]
bus_interfaces:
[
{
protocol: tlul
direction: device
}
]
}
```

The pkg file looks like:

```systemverilog
package block_reg_pkg;

// Address widths within the block
parameter int BlockAw = 2;

////////////////////////////
// Typedefs for registers //
////////////////////////////

typedef struct packed {
logic d;
} block_hw2reg_enable_reg_t;

// HW -> register type
typedef struct packed {
block_hw2reg_enable_reg_t enable; // [0:0]
} block_hw2reg_t;

// Register offsets
parameter logic [BlockAw-1:0] BLOCK_ENABLE_OFFSET = 2'h 0;

// Reset values for hwext registers and their fields
parameter logic [0:0] BLOCK_ENABLE_RESVAL = 1'h 0;
parameter logic [0:0] BLOCK_ENABLE_EN_RESVAL = 1'h 0;

// Register index
typedef enum int {
BLOCK_ENABLE
} block_id_e;

// Register width information to check illegal writes
parameter logic [3:0] BLOCK_PERMIT [1] = '{
4'b 0001 // index[0] BLOCK_ENABLE
};

endpackage
```

and the snippet of the RTL top level looks like:

```systemverilog
// Register instances
// R[enable]: V(True)
logic enable_qe;
logic [0:0] enable_flds_we;
assign enable_qe = &enable_flds_we;
prim_subreg_ext #(
.DW (1)
) u_enable (
.re (enable_re),
.we (enable_we),
.wd (enable_wd),
.d (hw2reg.enable.d),
.qre (reg2hw.enable.re),
.qe (enable_flds_we[0]),
.q (),
.ds (),
.qs (enable_qs)
);
```

Reproduce the issue with the supplied HJSON through regtool, then inspect the generated reg_top.sv and package output around the external ENABLE register and rw1c handling. Trace the hwext and rw1c entry points first; done means the generated RTL does not reference the nonexistent reg2hw.enable.re signal and provides a consistent implementation for the external register.

Written by the indexing model from the issue text.