[rom_ext] Lockdown
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- SystemVerilog
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Description
Lock down the chip before handing off to the owner stage.
- [ ] ePMP settings (see [#5653](https://github.com/lowRISC/opentitan/issues/5653))
- [ ] Flash controller
- [ ] certain data pages?
- [ ] certain info pages
- [ ] OTP controller.
- [ ] SRAM execution.
- [ ] Alert handler (should already be locked by ROM).
- [ ] Determine if there are any other chip HW that needs locking.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the ROM-to-owner-stage handoff and identify where the listed ePMP, flash, OTP, SRAM, and alert-handler controls are handled. Review the linked ePMP issue and document which hardware protections must be locked before handoff, including whether any additional chip hardware is missing; done means the required lockdown scope is established and implemented.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100