[sw] Find out why verilator fails to build after building english breakfast

Description

The following scenario does not work:

• build verilator for english breakfast (by using the english breakfast scripts)
• restore all modified files in the git tree
• then build verilator for earlgrey

I get the following error:

ERROR: %Warning-ASSIGNDLY: ../src/lowrisc_systems_ast_0.1/rtl/vcc_pgd.sv:39:33: Unsupported: Ignoring delay on this assignment/primitive.
   39 |     vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_RDLY) gen_supp_a;
      |                                 ^~~~~~~~~~~~
                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=4.210
                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.

This can be fixed by removing the autogenerated files in hw/top_englishbreakfast/ip/ast/rtl/ and hw/top_englishbreakfast/ip_autogen/.

Find out why removing those files is necessary. Pirmin thinks that fusesoc is selecting the wrong files

Reproduce the sequence using the English Breakfast scripts: build Verilator, restore the Git tree, then build Earlgrey. Compare the generated files in hw/top_englishbreakfast/ip/ast/rtl/ and hw/top_englishbreakfast/ip_autogen/ and inspect how FuseSoC selects them. Done means the Earlgrey build succeeds without manually removing those generated files.