lowRISC / lowRISC/opentitan

[chip,dv] rom integrity check failure need to be captured by TB

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#19,230 0 comments 0 reactions 0 assignees View on GitHub
Component:ChipLevelTest Component:DV Earlgrey-PROD Candidate Type:Enhancement Type:FutureRelease
Dominant language
SystemVerilog
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Description

### Description

When rom integrity check is failed by HW, in current earlgrey testbench,
booting is hold and test is failed by global timeout.
Need to add monitor to capture this event for better visibility.

Contributor guide

Open the contributing guide

Research direction

Start in the earlgrey testbench and trace how a ROM integrity check failure currently leads to boot being held and the global timeout. Add a monitor for this event so the testbench reports the failure directly instead of relying on the timeout.

Written by the indexing model from the issue text.

Assessment

Domain
testing-qa
Issue type
Feature
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
42/100

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