lowRISC / lowRISC/opentitan

[pwrmgr] Error FSM state is not observable in pwrmgr_fsm

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#19,124 8 comments 0 reactions 0 assignees View on GitHub
Earlgrey-PROD Candidate Priority:P2
Dominant language
SystemVerilog
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Description

### Description

## Description

The pwrmgr_fsm implements a sparsely encoded state machine. All deviations from the valid state, e.g., due to a fault on the state register, lead the FSM to transfer to the `default` state.

However, compared to other FSMs, the particular FSM does not implement a dedicated error signal for this FSM. Consequently, it is impossible to observe if the error state is entered.

## Potential Solution

Implement a dedicated error signal for the FSM that asserts if the FSM reaches the default state.

Contributor guide

Open the contributing guide

Research direction

Start by locating the pwrmgr_fsm implementation and compare it with other FSMs that expose a dedicated error signal. Add an observable signal that asserts when the FSM enters its default state, then verify that invalid-state behavior and the signal are covered by the existing pwrmgr tests.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Feature
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
45/100

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