[i2c,dv] i2c_host_fifo_full_vseq changes

Description

There is a suggested modification to the FIFO full sequence: send N + 1 items (N is fifo depth), configure agent to slow read mode (not able to completely handle one item before N+1 items are written), then check fifo_full bit is:

• not asserted when N items are written to fifo (fifo_lvl = N-1)
• asserted once writing one more item to fifo (fifo_lvl = N)
• clear interrupt, finish processing all the items and check interrupt not asserted

Based on this TODO:
https://github.com/lowRISC/opentitan/blob/c342c8c6bf2d014bc69b14691514e69b28962a18/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_full_vseq.sv#L49-L54

I am putting this in the icebox because the current test sends a random number of transactions with a random number of bytes and checks that the FIFO level, empty and full signals are exercised the right way. The FIFO full level is hit when number of transactions times number of bytes is greater than 64, the FIFO depth. Number of transactions varies from 10-20 and bytes varies from 1-32 so we will hit these interesting cases with reasonable likelihood without making a directed test case for it.

Start by reading hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_full_vseq.sv, especially the TODO at lines 49-54, and compare it with the current randomized checks. The work is complete when the sequence covers the N, N+1, interrupt-clear, and final-processing FIFO checks described in the issue.