[rv_timer] Align interrupt behavior with privileged spec
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@GregAC is already working on this.
Since Apr 2, 2024.
Component:RTL
Earlgrey-PROD Candidate
IP:rv_timer
Priority:P2
Type:FutureRelease
- Dominant language
- SystemVerilog
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Description
Description
The interrupt currently is cleared for any write to mtimecmp, but this was a misinterpretation of the spec. Ensure the interrupt is asserted as long as mtime is greater than or equal to mtimecmp, with no glitching.
While implementing this change, take advantage of the expanded interrupt capabilities, and convert the rv_timer interrupt to the Status type to avoid awkward latching behavior.
From https://github.com/lowRISC/opentitan/issues/18400#issuecomment-1590249373
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