[i2c,dv] Check I2C timing compliance via a SVA-based protocol checker
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Component:DV
Earlgrey-PROD Candidate
IP:i2c
Priority:P2
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Description
This issue is here to track the work required to add assertions to the test bench. For example, SDA should not change at the same time as SCL, which caused the following issue: https://github.com/lowRISC/opentitan/issues/18718
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files or tests are named. Start by locating the I2C test bench and reading issue #18718 for the reported timing failure; define the required SVA checks for I2C timing compliance and verify that the test bench detects violations such as SDA changing with SCL.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100